The continuing trend of scaling down integrated circuits has motivated the semiconductor industry to consider new techniques for fabricating precise components at sub-micron levels. In dynamic random access memory (DRAM) devices it is essential that storage node capacitor cell plates be large enough to exhibit sufficient capacitance in order to retain an adequate charge in spite of parasitic capacitance and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate.
The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices. The ability to densely pack memory cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One area of DRAM technology is the development of a two-transistor memory cell such as taught in U.S. Pat. No. 5,122,986, by Lim or in U.S. Pat. No. 6,438,016 B1, by Keeth et al., both of which are incorporated by reference, as if set forth in their entirety. U.S. Pat. No. 5,122,986 shows the utilization of a data read transistor and a data write transistor that are coupled such that a storage node is developed by a parasitic capacitance between the source/drain electrode of the write transistor and the control gate of the read transistor. U.S. Pat. No. 6,438,016 B1 shows the utilization of a storage cell comprising a storage capacitor coupled to the drain of a (data) read/write transistor and to the drain of a (data) refresh transistor.
U.S. Pat. Nos. 5,122,986 and 6,438,016 B1 utilize a two-transistor memory cell, where U.S. Pat. No. 5,122,986 develops a storage node using parasitic capacitance between the two-transistors of the memory cell, while U.S. Pat. No. 6,438,016 B1 develops an actual storage capacitor between the two-transistor memory cell.
Utilizing a two-transistor memory cell in a DRAM device requires that the memory cell structure be scaled to meet the density requirements of current and future die size, while maintaining sufficient charge storage capability of the storage capacitance.
The present invention describes a capacitor structure and a method to form the capacitor structure that addresses the above challenges.